Description

HPE is accepting resumes for VLSI Engineer II in Sunnyvale, CA (Ref.10022975). Implement digital circuit’s micro-architecture design in RTL (Verilog/System Verilog) using common design schemes: flops, arbiters, FIFOs, memories, finite state machines, etc. Integrate 3rd party IP design into Juniper’s ongoing ASIC projects. Part-time telecommuting allowed. Salary Range: $155,368.80/year to $213,500.00/year. Variable incentives may also be offered. Information about employee benefits offered can be found at https://myhperewards.com/main/new-hire-enrollment.html. E-Mail resume to [email protected]. Include Ref. #, full name, email & mailing address. No phone calls. Must be legally authorized to work in U.S. w/out sponsorship. EOE.